The semiconductor integrated circuit (IC) industry has experienced rapid growth. In semiconductor manufacturing, functional density is generally increasing with reduced geometry size, and smaller and more complex integrated circuits than the previous generation are produced. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, such scaling down also increases the processing and manufacturing complexity of integrated circuits. For these advances to be realized, associated developments are required in the processing and manufacturing of the integrated circuits.
For example, as IC technologies are continually progressing to smaller technology nodes, such as 65 nm technology node, 45 nm technology node, 20 nm technology node and below, simply scaling down similar designs used at larger feature sizes often results in poorly shaped or poorly arranged device features. Typically, optical proximity correction (OPC) may be performed on a design pattern before the pattern is created on a mask. Nevertheless, current OPC techniques may not offer great enough fidelity or sufficient rules to correct problems in sub-45 nm designs. Therefore, although existing methods for improving IC manufacturing have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.